State of the art microprocessor designs continue to integrate operation-specific execution units (e.g. pixel-processing units, floating-point dividers and multipliers) on a single chip. Since these operation-specific execution units are tuned to perform specific tasks, their use typically improves a microprocessor's overall performance. The drive for higher performance is especially evident in floating-point computations, and typically, superior floating-point performance is key to microprocessor competitiveness. Among the problems associated with floating-point computations is the handling of mantissa overflow, mantissa postnormalization, and exponent adjustment in the execution of floating-point addition and subtraction operations. This invention provides a method for performing these functions in a unified manner that simplifies the logic and removes critical paths.
The algorithm for floating-point addition and subtraction is well understood. The required operations is performed in five steps which are as follows: (1) Align the operands; (2) Add/Subtract the two mantissas; (3) Postnormalize: (a) if the result of the addition/subtraction overflows, then shift the mantissa right one bit place and increment the exponent; or (b) remove the leading zeros of the addition/subtraction result by performing a left shift, and decrementing the exponent by an amount equal to the number of leading zeros; and (4) A rounding operation is then performed by rounding the result from the postnormalization stage according to the rounding mode; if the mantissa overflows as a result, shift right one place and increment the intermediate exponent. Lastly, the result is checked for exponent underflow/overflow.
FIG. 1 illustrates a data processing system 10 having a conventional floating-point adder unit 32 for performing a floating-point addition/subtraction operation. Illustrated in FIG. 2 is a block diagram of a known floating-point adder unit 32. Typically, operand select/alignment logic 36 aligns the binary points of two floating-point numbers (OPERAND A, OPERAND B), received from the source busses 33, so that the exponents of the floating-point numbers will be equal in magnitude. This is accomplished by shifting the mantissa of the floating-point number with the smaller exponent to the right by a number of bit positions equivalent in magnitude to the exponent difference between the two floating-point numbers. The appropriately aligned mantissa values are shown entering the mantissa adder 44, while the larger exponent is selected by an initial exponent multiplexor as the initial exponent result. The operand select/alignment logic 36 may swap the mantissa values (MANTA and MANTB) to insure that in cases of an effective subtraction, the smaller mantissa value is subtracted from the larger mantissa value. This ensures that the result from the mantissa adder 44 is always a positive result, and hence will not require complementation. The mantissa adder 44 adds the two mantissa values (MANTA and MANTB) to generate an initial mantissa sum and a carry output signal.
In cases of effective addition, the output of the mantissa adder 44 may overflow. A right shifter 48 is used to shift the mantissa sum to the right by one bit position. A mantissa sum multiplexor 50, controlled by the carry output from adder 44, is used to select a prenormalized mantissa sum from either the right-shifted mantissa value or the initial mantissa sum. In parallel with the mantissa addition, the initial exponent is incremented by exponent increment adder 42 to generate an incremented exponent. An exponent increment multiplexor 46, also controlled by the carry output from adder 44, selects an intermediate exponent value from either the initial exponent or the incremented exponent.
In cases of effective subtraction, the output of the mantissa adder 44 must be normalized by eliminating any leading zero-bits in the prenormalized mantissa sum selected by the mantissa sum multiplexor 50. For each bit position that the prenormalized mantissa sum is shifted to the left, the exponent must be decremented by one. The leading-zero-detect logic 52 inspects the prenormalized mantissa sum to determine the number of leading zeros. The encoded output of the leading-zero-detect logic 52 is used to control the normalizer 54 (for left shifting the prenormalized mantissa sum), and is provided as an input to exponent adjust adder 58 (for adjusting the exponent value). The exponent adjust adder 58 subtracts the number of leading zeros (determined by the leading-zero-detect logic 52) from the intermediate exponent.
Once the normalization has been performed, the rounding operation proceeds. Depending upon the current rounding mode and any guard bits resulting from the mantissa alignment performed by the operand select/alignment logic 36, the rounding logic control 68 provides a ROUND control signal, indicating whether or not the mantissa should be incremented, to an adder 66. Accordingly, the ROUND signal can be used as the carry-in to adder 66 to effectively increment the mantissa, thereby generating a "rounded" mantissa. It is possible, therefore, that the rounded mantissa may overflow necessitating a right-shifting of the mantissa by one bit position, and the incrementing of the exponent. These functions are implemented via a right shifter 76 and exponent round adder 60, respectively. The exponent result multiplexor 62 and rounded mantissa result multiplexor 74 are used to select the result exponent, and postnormalized mantissa, respectively.
In FIG. 2, it should be noted that known optimizations are incorporated into adder 32 to improve performance. For example, in both cases where the mantissa may overflow, the exponent value is unconditionally incremented by adders 42 and 60, and the intermediate and result exponent values, respectively, are selected based upon the adder carry outputs (provided by mantissa adders 44 and 66) which control the associated exponent multiplexors 46 and 62, respectively. These optimization improve the performance of the adder unit 32 as compared to a slower alternative in which the carry outputs of the mantissa adders 44 and 66 are fed directly into the exponent adders 42 and 60, respectively, to control the incrementing of the exponent values.
The exponent result multiplexor 62 provides the exponent result to the exception detection logic 70. If an exception condition is detected, then the exception detection logic 70 will provide a default value (e.g. 80-bit result) to the write-back multiplexor 76. If no exception conditions exist, the exception detection logic 70 will provide a control signal to the write-back multiplexor 76, thereby allowing the multiplexor to transfer the result exponent value along with the postnormalized mantissa and a sign bit ("normal" result) to the register file 26. Thus, the default value or the normal result, as the case may be, is written back to the register file 26, via the write-back busses 34.
The implementation of adder unit 32 has several disadvantages. The first disadvantage involves the handling of mantissa overflows. For example, the carry output of adder 44, must drive both the mantissa sum multiplexor 50 and exponent increment multiplexor 46. This results in significant loading on the critical carry output signal (e.g. 80-bits of two-input multiplexors for IEEE double extended precision floating-point numbers), and therefore, will limit the add cycle time. The second disadvantage involves the critical path from the output of the leading zero detect logic 52 through the exponent adjust adder 58, and the exponent round adder 60--the output of which feeds the exponent result multiplexor 62. Essentially, in adder unit 32, the critical path formed to generate the exponent result value provides a major limitation on the add cycle time.
Thus, it is desirable to provide a unified method for postnormalization of floating-point operands which maximizes performance, while minimizing the necessary logic required for implementation of the method.